15. The Circuit Model

15.1Circuit Notation

A quantum circuit is a left-to-right timeline. Horizontal lines are qubits; boxes on the lines are gates; time flows left to right; the right edge is always measurement. Two-qubit gates are drawn as a dot (control) connected by a vertical line to the gate (target). Barriers (||) forbid reordering; double lines after measurement carry classical bits. The notation is gloriously informal across papers — that is a feature to be aware of, not a bug: always reconstruct a paper's circuit from its accompanying matrix or code. Our parser (17.10) will accept a text form of this notation, so you will internalize it twice: visually and programmatically.

q0 ──■────H──M
     │       ║
q1 ──X───────M
             ║
c0 ─────────╩═
c1 ───────────

15.2Wires

A wire is a qubit's entire life: prepared, operated on, and measured. Wires are not physical wires — on superconducting chips a "wire" is a resonator-mediated coupling, on trapped ions it is the shared motional mode — but the abstraction is precise: a wire carries quantum state, and touching it is the only way to affect it. Two truths to internalize early. First, identity is not idleness: a wire with nothing on it still decoheres. Second, wires can be swapped logically (SWAP gate) at a cost, which is why connectivity (15.10) dominates real circuit costs.

15.3Gates

Gates are unitary operators drawn as boxes. The standard table you must know cold: X (bit flip), Y, Z (phase flip), H (Hadamard, basis change), S, T (phase gates), RX/RY/RZ (rotations by angle θ), and the two-qubit CX/CZ plus SWAP. From Part V you know H, CX on |00⟩ makes entanglement; the circuit model packages that fact as a drawing. Gates do not exist physically — they are calibrations of shaped pulses (Part XI) — so "the same" gate on different hardware differs in fidelity and duration. Gate fidelity numbers (99.9% single, 99.5% two-qubit, best-in-class 2025) are the currency of every cost estimate in Part VII.

15.4Measurements

Measurement is drawn as a meter (or an arc with an arrow) and is not a gate: it is non-unitary, irreversible, and it produces a classical bit. Mid-circuit measurement — measuring a qubit and continuing to use it — is supported on modern hardware and is the enabling primitive for QEC (Part X), teleportation, and dynamic circuits. Measure in bases other than Z by conjugating: H then measure is an X-basis readout. The measurement layer is where quantum meets classical control flow: if c0: apply X — real-time classical feedback — is the seed of every fault-tolerant protocol.

15.5Initialization

Every wire starts somewhere, and the somewhere is |0⟩ — prepared by cooling qubits to their ground state (tens of millikelvin for superconducting, near-absolute-zero ions, room-temperature photons with caveats). Initialization fidelity is usually the best number on any hardware datasheet (99.99%), and it matters more than beginners assume: garbage in, garbage out, at exponential amplitude-blowup cost. Reset operations — mid-circuit returns to |0⟩ — exist in Qiskit and on hardware, enabling qubit reuse. Building |ψ⟩ states beyond |0⟩ is itself a circuit-design task: state preparation is a real cost (O(2ⁿ) gates in the general case) that naive resource estimates forget.

15.6Circuit Execution

Executing a circuit means: initialize, apply gates in time order (in parallel where wires are independent), measure, repeat N times ("shots"), and histogram the outcomes. Between "circuit as written" and "circuit as executed" sits the whole compilation pipeline (Part XII): transpile to the backend's gate set, route around connectivity limits, schedule against decoherence. Execution on hardware is remote (cloud queues), slow (minutes per job), and noisy — which is why 90% of your work will use simulators, with hardware reserved for validating that your noise model isn't lying to you. Part VII's experiments follow exactly that discipline.

15.7Circuit Depth

Depth is the length of the longest path through the circuit — the number of sequential time steps assuming unlimited parallelism. Depth × gate time ≈ how long the circuit runs, and since coherence is finite, depth is the enemy: T1/T2 budgets (tens to hundreds of microseconds for superconducting) cap the depth you can afford, which caps the algorithms you can run. Two circuits with identical gate counts can differ 10× in depth depending on scheduling. When papers quote complexity, they quote depth (usually in two-qubit gates); when you design circuits, you minimize it: parallelize, commute gates past each other, and let the compiler (Part XII) do the rest.

15.8Gate Count

Gate count is total operations — usually reported separately for one-qubit and two-qubit gates, because two-qubit gates are 5–10× slower and noisier. Shor for RSA-2048: ~5 trillion Toffoli-class gates in early estimates, under 1 million with modern optimizations; Grover for AES-128: ~2⁶⁴ iterations (huge). Gate count is what algorithmic complexity theory actually counts; depth is what hardware cares about; the ratio depends on scheduling and connectivity. Learn to read resource-estimate papers with both eyes: "2⁹⁶ T gates" and "T factory + logical qubits" (Part X) tell you what machine the estimate assumes.

15.9Qubit Count

How many wires does the problem need? Three numbers usually quoted: data qubits (the register), ancilla qubits (workspace, 15.11), and physical-per-logical overhead (100–1000+ in surface codes, Part X). IBM's Starling targets ~200 logical qubits from ~200,000 physical ones by 2029 — that overhead factor (~10³) is the single most important number in the field's roadmap, and it is why "we need a million qubits" headlines translate to "we need a few hundred useful ones." Resource estimates stack all three: algorithm qubits × overhead + routing + magic-state distillation. Practice reconstructing that arithmetic; it is how you read every roadmap announcement critically.

15.10Connectivity

Real hardware has a coupling map: qubit i can entangle only with its neighbors (heavy-hex lattice for IBM, square lattices for Google, all-to-all within an ion trap). Algorithms assume all-to-all; hardware does not provide it; therefore routing — inserting SWAPs to move states next to their gates — is a major compiler pass (Part XII), and SWAP overhead can dominate circuit cost on sparse lattices. Depth 10 all-to-all can become depth 100 on heavy-hex. When choosing a backend, check its coupling map first; when reading a benchmark, ask what connectivity it assumed. Cloud backends in Qiskit expose this as backend.coupling_map.

15.11Ancilla Qubits

Ancillas are workspace qubits: not the answer, but essential to the computation. Uses: computing a function reversibly (compute-copy-uncompute pattern, Ch. 18), phase kickback (Ch. 24), syndrome extraction in QEC (Part X), magic-state distillation, and qubit reuse (measure-and-reset). Clean ancillas — returned to |0⟩ after use — are a contract; leaving them entangled with your data register is a classic bug (your simulator's probabilities will look wrong in a way that's hard to diagnose). Distinguishing "data," "clean ancilla," and "dirty ancilla" in circuit comments is a habit worth starting now, before Part X makes it survival-critical.

15.12Reversible Computation

Since all quantum gates are unitary, all quantum computation is reversible — so classical logic must be compiled into reversible form to run on a quantum computer. The recipe: compute f(x) into an ancilla with Toffoli networks (f AND-gates), then either measure the ancilla (phase oracle) or uncompute it back (phase-free). The overhead: one ancilla per AND, plus uncomputation, roughly 2× the classical gate count and +1 qubit per intermediate bit. Bennett's 1973 construction founded this field; today it is the bread-and-butter of oracle construction for Grover and of arithmetic for Shor (Ch. 26). You will build reversible adders in Chapter 17's project extension.