44. From Algorithm to Hardware
44.1Logical Circuit
The pipeline's front door: the algorithm-level circuit as written in Part VII — arbitrary gate sets, all-to-all connectivity, no noise. This "logical circuit" is a fiction, but a load-bearing one: it is the interface between algorithm designers and everything below. Its units of account are abstract (T gates, Toffolis, arbitrary rotations); its assumptions (uniform connectivity) are exactly what hardware violates. The compiler's job, formally stated: transform the fiction into a schedule of native operations on physical qubits, minimizing a cost function (depth, two-qubit count, T-count, expected error) while preserving the unitary (up to global phase) — and later, in fault-tolerant machines, doing all of it at the logical layer instead.
44.2Hardware Constraints
The non-negotiables a compiler must respect. Finite coherence: T1/T2 of tens–hundreds of microseconds cap total circuit duration. Gate errors: ~0.1% one-qubit, ~0.3–1% two-qubit — error budgets, not absolutes: a 1,000-gate circuit on 0.5% two-qubit errors has almost no signal left. Limited connectivity: degree 2–3 per qubit on superconducting lattices. No mid-circuit branching (mostly): control flow is classical-post or limited dynamic circuits. Calibration drift: today's optimal schedule is tomorrow's mediocre one. And the meta-constraint: all constraints bind simultaneously — optimizing depth into a fidelity cliff is a classic beginner pass.
44.3Gate Sets
Every backend exposes a native gate set: IBM's {RZ, SX, X, ECR/CZ}, ion traps' {arbitrary R rotations, MS gates}, Google's {sqrt(X), CZ}. Universal sets (Part III) guarantee expressiveness; efficiency differs hugely — circuits on ion traps compile with fewer two-qubit gates (all-to-all helps) but slower gate clock. The compiler's basis-translation pass maps your gates onto natives, and the choice among equivalent decompositions (two CX vs three CZ equivalents, rotation merging) is where real depth is won. T-gates deserve special billing: in fault-tolerant machines they are the expensive non-Clifford resource, so T-count is the metric algorithm optimizers chase (28.7's qubitization is the champion).
44.4Connectivity
The coupling graph is a hardware fact: IBM heavy-hex (degree 2–3), Google square grid, trapped-ion all-to-all (within a trap), neutral-atom reconfigurable (atoms moved optically!). Compiler consequence: any gate between non-adjacent qubits needs routing — SWAP insertion or state teleportation — and on heavy-hex, routing overhead routinely doubles–triples circuit depth. The mapping problem (44.7/45.7): which logical qubit lands on which physical qubit — is NP-hard, heuristic-solved (SABRE in Qiskit), and sensitive enough that good mapping alone can halve your error rates. For ion traps the problem inverts: routing is free, but the linear trap makes two-qubit gates queue.
44.5Native Gates
Native gates are what the control electronics actually implement — shaped microwave or laser pulses calibrated per qubit, per gate, per day. Everything else is a lie the compiler tells in their language. Properties to track: fidelity (per-qubit, per-gate), duration (35 ns X gates, ~300–600 ns two-qubit, ~600 ns measurement on transmons), and spectator errors (gates on neighbors perturb idling qubits — real compilers increasingly schedule around it). The abstraction is leaky in both directions: below it, optimal-control research designs better pulses; above it, circuit optimization must not destroy patterns the pulse layer implements well (e.g. echoed cross-resonance).
44.6Circuit Decomposition
Turning abstract gates into native ones, optimally. Known results: any n-qubit unitary needs O(4ⁿ) two-qubit gates in general (Shende–Markov–Bullock), so structure is everything — controlled rotations, multi-controlled Toffolis (L-method, ~100 basic decompositions in Qiskit's library each with different gate-count/depth/ancilla tradeoffs), Pauli exponential rotations (the workhorse of chemistry circuits, Ch. 48), and ZX-calculus-based synthesis (the 2020s' sharpest tool — PyZX rewrites circuits as graph-like diagrams and synthesizes back with provably near-optimal two-qubit counts). Decomposition is where math meets compiler engineering most directly; ZX-calculus fluency is a differentiator for anyone entering compiler research.
44.7Scheduling
Given a routed, native-gate circuit, produce a timeline: which gate starts when, on which control channel, respecting dependencies and hardware timing rules. ASAP/ALAP schedules give depth bounds; insertion of delays is unavoidable because parallelism is imperfect — and every delay is decoherence time bought and paid for. Advanced scheduling is noise-aware: align idle qubits with dynamical decoupling sequences (44.8), respect crosstalk groups, order gates to keep fragile states short-lived. Timing on real hardware is measured in nanoseconds against a shared reference clock — a domain where quantum engineering collides head-on with classical digital design, and the skill transfer for RTL-background engineers is nearly total.
44.8Pulse-Level Control
Below gates live pulses: the actual waveforms (Gaussian-square flux tones, DRAG-corrected microwave envelopes) whose area and phase implement rotations. Qiskit exposes this layer (pulse schedules, now folding into the Qiskit Dynamics ecosystem), and it matters in three places: calibration (Rabi/Ramsey experiments are pulse experiments — Part XI), optimization (shorter/better pulses directly raise fidelity), and dynamical decoupling (XY4/CPMG pulse sequences inserted into idle periods cancel low-frequency noise — a compiler pass that runs physics, not algebra). You cannot touch hardware pulses from a laptop without an account, but Aer models their imperfection, and Chapter 17's simulator can, too. Pulse literacy separates serious compiler work from toy compilers.